Overview
As a Lead Member of Technical Staff Logic Design Engineer, you will shape secure silicon IP within Rambus’s Silicon IP team. You’ll lead digital design efforts, guide project plans, and drive RTL implementation and verification for high-value products. You collaborate across engineering, product management, and sales to ensure robust, secure IP that scales with data-centric workloads. This role offers hands-on technical leadership in a fast-paced, interdisciplinary R&D environment with a hybrid work model.
Arbeidsvoorwaarden / Benefits
- hybrid work arrangement
- competitive compensation package
- base salary, bonus, equity
- employee benefits
Verantwoordelijkheden
- Lead digital designers and manage project plans and effort estimates
- Architect block specifications and contribute to IP innovation and patent activity
- Perform RTL design, linting, CDC analysis, synthesis, and IP release
- Coordinate verification with planning, simulation, formal verification, and documentation
- Contribute to development flow and methodologies within a dynamic R&D group
- Engage with technical leaders and cross-functional teams to drive high-value product development
Belangrijkste vereisten
- BS or MS in Hardware Engineering, Computing Science or equivalent
- Eight+ years in security or chip industry in relevant R&D roles
- Deep knowledge of SoC, silicon IP and/or FPGA logic design flows
- Strong Verilog, VHDL, SystemVerilog and scripting skills
- Strong written and verbal communication; capable of explaining concepts to technical audiences
- Good documentation skills in text and drawings
- Analytical thinking
- Creative problem-solving
- Team-oriented and collaborative mindset
- Verilog
- VHDL
- SystemVerilog
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