Overview
In this role you verify Snap’s AI ASIC designs for Spectacles, ensuring high-quality wearables and edge AI IP. You own complex IP blocks, drive verification across the project lifecycle, and collaborate cross-functionally to accelerate debugging. You’ll shape verification methodologies and push best-in-class practices in a fast-paced, international hardware team. This is a chance to contribute to cutting-edge AR hardware at scale and impact product launches.
Arbeidsvoorwaarden / Benefits
- paid parental leave
- comprehensive medical coverage
- emotional and mental health support programs
- phone and gym allowances
- flexible "Default Together" hybrid work policy
- competitive compensation packages
Verantwoordelijkheden
- Assure overall design quality for Spectacles wearable devices
- Take ownership of complex IP blocks and edge AI/camera/display IP verification
- Drive project lifecycle from spec influence to advanced UVM environments and coverage sign-off
- Collaborate cross-functionally to refine requirements and accelerate debugging
- Shape and launch new verification methodologies and initiatives
Belangrijkste vereisten
- 5+ years in state-of-the-art verification methodologies (UVM, SystemVerilog, constraint-random verification, coverage-driven sign-off)
- Experience using AI tools to automate and improve verification
- Deep technical expertise in NPUs, image/video processing pipelines, or custom silicon architectures
- Proven ability to build sophisticated UVM test environments for custom IPs, ideally with Synopsys front-end suites
- Knowledge of verification for peripherals in image/video processing (e.g., MIPI)
- Fluency in RTL (SystemVerilog, Verilog, VHDL) and clean code practices
- Experience with CI/CD workflows and Git
- Strong interpersonal, communication, and independent, fast-paced work style
- interpersonal skills
- leadership
- collaboration
- UVM
- SystemVerilog
- constraint-random verification
ASIC Verification Engineer in Eindhoven werkgever: Jobrapido
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